A continuing goal of integrated circuit design is to increase integration density, and a corresponding goal is to reduce the footprint of specific circuit components. One component commonly utilized in integrated circuits is a transistor. In some applications, paired transistors may be utilized in CMOS (complementary metal oxide semiconductor) constructions, with one of the transistors being PMOS (p-type metal oxide semiconductor) and the other being NMOS (n-type metal oxide semiconductor).
FIGS. 1-3 illustrate an example prior art semiconductor device 900 comprising a PMOS region 902 paired with an NMOS region 904.
The PMOS region 902 includes a pair of gate electrodes 913, and includes diffusion regions 910-912 adjacent the gate electrodes. The diffusion regions correspond to source/drain regions. In some applications, diffusion region 911 is a drain region, and diffusion regions 910 and 912 are source regions. The gate electrodes 913 and diffusion regions 910-912 together form a PMOS transistor 905, which is approximately demarcated with a dashed line 903.
Wiring 914 (for instance, WLIC1 connected to power supply voltage Vdd) is provided proximate the PMOS transistor 905, and is electrically coupled to the outer source/drain regions 910 and 912 through contacts 915 (the contacts are shown with dashed-lines to indicate that they are under other wiring). Additional wiring 916 (for instance, WLIC3) connects to the inner source/drain region 911 through contacts 917. The contacts 915 and 917 may extend through insulative material 918 (shown in FIGS. 2 and 3).
The NMOS region 904 includes a pair of gate electrodes 923, and includes diffusion regions 920-922 adjacent the gate electrodes. The diffusion regions correspond to source/drain regions. In some applications, diffusion region 921 is a drain region, and diffusion regions 920 and 922 are source regions. The gate electrodes 923 and diffusion regions 920-922 together form an NMOS transistor 925, which is approximately demarcated with a dashed line 923.
Wiring 924 (for instance, WLIC2 connected to power supply voltage Vss) is provided proximate the NMOS transistor 925, and is electrically coupled to the outer source/drain regions 920 and 922 through contacts 935. Additional wiring 926 (for instance, WLIC3) connects to the inner source/drain region 921 through contacts 937.
The PMOS and NMOS regions 902 and 904 are supported by a semiconductor substrate 940 (shown in FIGS. 2 and 3). Such semiconductor substrate may comprise, for example, monocrystalline silicon and/or any other suitable semiconductor material. The substrate is shown to comprise a p-type background-doped region 942, and to comprise an n-type doped n-well 944 extending into the p-type doped region. The source/drain regions 910-912 of the PMOS device are within the n-well 944; and the source/drain regions 920-922 of the NMOS device are within the p-type background-doped region 942.
A problem with the prior art design of device 900 can be that parasitic resistance undesirably occurs in the PMOS device along the source diffusion regions 910/912 (as diagrammatically illustrated with resistors 950). Similar parasitic resistance may also problematically occur with respect to the NMOS device, although such is not specifically illustrated in FIG. 1.
It is desired to develop improved devices which alleviate or prevent the problematic parasitic resistance described above. It is also desired to develop improved devices having relatively small footprints suitable for incorporation into highly integrated circuitry.